However, the growth direction did not affect the wettability of the surface.  https://www.selleckchem.com/products/suzetrigine.html  Vertically grown nanorods can still affect optical transmittance because they facilitate the propagation of light. In the case of Corning glass, superhydrophobic surfaces with contact angles of 150° and 152.3° were formed on both samples with buffer layers of 50 nm and 100 nm, respectively. Therefore, a buffer layer thickness in the range of 50-100 nm is suitable for realizing a transparent superhydrophobic surface on a glass substrate.We demonstrated the enhancement of the retention characteristics in solution-processed ferroelectric memory transistors. For enhanced retention characteristics, solution-processed Indium Gallium Zinc Oxide (InGaZnO) semiconductor is used as an active layer in a dual-gate structure to achieve high memory on-current and low memory off-current respectively. In our dual-gate oxide ferroelectric thin-film transistor (DG Ox-FeTFT), while conventional TFT characteristic is observed during bottom-gate sweeping, large hysteresis is exhibited during top-gate sweeping with high memory on-current due to the high mobility of the InGaZnO. The voltage applied to the counter bottom-gate electrode causes variations in the turn-on voltage position, which controlled the memory on- and off-current in retention characteristics. Specifically, due to the full depletion of semiconductor by the high negative counter gate bias, the memory off-current in reading operation is dramatically reduced by 10⁴. The application of a high negative counter field to the dual-gate solution-processed ferroelectric memory gives a high memory on- and off-current ratio useful for the production of high performance multi-bit memory devices.We developed self-assembled hybrid dielectric materials via a facile and low-temperature solution process. These dielectrics are used to facilitate ultralow operational voltage of organic thinfilm transistors. Self-assembly of bifunctional phosphonic acid and ultrathin hafnium oxide layers results in the self-assembled hybrid dielectrics. Additionally, the surface property of the top layer of hafnium oxide can be tuned by phosphonic acid-based self-assembled molecules to improve the function of the organic semiconductors. These novel hybrid dielectrics demonstrate great dielectric properties as low-level leakage current densities of 105, threshold voltage 0.5 V).We investigate the effects of environmental conditions on the electrical stability of spin-coated 5,11-bis(triethylsilylethynyl)anthradithiophene (TES-ADT) thin-film transistors (TFTs) in which crosslinked poly(4-vinylphenol-co-methyl methacrylate) (PVP-co-PMMA) was utilized as a gate insulator layer. Atomic force microscopy observations show molecular terraces with domain boundaries in the spin-coated TEST-ADT semiconductor film. The TFT performance was observed to be superior in the ambient air condition. Under negative gate-bias stress, the TES-ADT TFTs showed a positive threshold voltage shift in ambient air and a negative threshold voltage shift under vacuum. These results are explained through a chemical reaction between water molecules in air and unsubstituted hydroxyl groups in the cross-linked PVP-co-PMMA as well as a charge-trapping phenomenon at the domain boundaries in the spin-coated TES-ADT semiconductor.High-k Y₂O₃ thin films were investigated as the gate dielectric for amorphous indium zinc tin oxide (IZTO) thin-film transistors (TFTs). Y₂O₃ gate dielectric was deposited by radio frequency magnetron sputtering (RF-MS) under various working pressures and annealing conditions. Amorphous IZTO TFTs with SiO₂ as the gate dielectric showed a high field-effect mobility (μFE) of 19.6 cm²/Vs, threshold voltage (Vth) of 0.75 V, on/off current ratio (Ion/Ioff) of 2.0×106, and subthreshold swing (SS) value of 1.01 V/dec. The IZTO TFT sample device fabricated with the Y₂O₃ gate dielectric showed an improved subthreshold swing value compared to that of the IZTO TFT device with SiO₂ gate dielectric. The IZTO TFT device using the Y₂O₃ gate dielectric deposited at a working pressure of 5 mtorr and annealed at 400 °C in 6 sccm O₂ for 1 hour showed a high μFE of 51.8 cm²/Vs, Vth of -0.26 V, Ion/Ioff of 6.0×10³, and SS value of 0.19 V/dec. With the application of a Y₂O₃ gate dielectric, the Vth shift improved under a positive bias stress (PBS) but was relatively unaffected by negative bias stress (NBS). These shifts were attributed to charge traps within the gate dielectric and/or interfaces between the channel and gate dielectric layer.Currently, the semiconductor manufacturing industry is seeing rapid movement from 2D planar to 3D FinFET technology. Among SCE-enhanced scaled fin structures, depending on stress engineering to increase mobility, merged elevated source-drain (eSD) epi structures are widely used because they can maximize device performance by reducing Rsd. While there is active research on device and epi own defects related to eSD process, there is no study on yield effect. Smart manufacturing (SM) applications, which form the core of Industry 4.0, are difficult to find in bulk-FinFETs, and it is difficult to find hidden systematic defects of complex three-dimensional structures using limited analyses such as in-line monitoring and abnormal trend detection. In this study, we investigate the root-cause of gate to eSD short, which is the primary FinFET yield detractor, and we obtain an optimized solution to improve yield by 25.2% without performance degradation. These improvements are accomplished using our in-house SM platform that consists of four components a virtual integration (VI) module for defining defects such as physical connection, void, and not open; a hot spot module for identifying the location of needed process control; an advanced analytics module including algorithms for selecting key features and predicting the fail bit; and an optimizer module that can co-optimize yield and performance.Electrohydrodynamic (EHD) jet printing enables rapid prototyping high-resolution and low-cost lines with width of micrometer or even nanometer. However, EHD printing always suffers from nozzle clogging when the nozzle inner-diameter decrease to micro-scale. Thus fabrication of low cost nozzles becomes significantly important. In this work, 50 μm wide and 12.5 μm deep PMMA (Polymethyl Methacrylate) nozzles were fabricated without using traditional expensive glass capillary pulling approach. To replicate PMMA nozzle with high precision, the embossing condition was optimized according to replication precision, the deformation rate, and maximum stress. To nearly fully bond PMMA nozzle with intact PMMA microchannel, the bonding condition was optimized according the bonding rate and dimension loss of PMMA microchannel. The availability of the fabricated PMMA nozzle was finally verified by EHD printing experiments.